October 31, 2022. – T2MIPs, the independent global supplier of semiconductor IP cores and technology experts, is pleased to announce the immediate availability of its partner’s proven and mature silicon MIPI DSI and CSI Tx-Rx Controller IP Cores with matching PHYs in major Fabs and nodes as small as 7nm. These MIPI cores have been in production in multiple chipsets with ultra-fast display and camera interface for high quality resolutions up to 4K for Next Gen products.
MIPI DSI Tx-Rx Controller IP Cores a flexible and fast interface for platforms such as smartphones, tablets, computers, cars and other screens and MIPI CSI Tx-Rx Controller IP Cores is a fast protocol commonly used to send static and moving images from cameras to application processors. Both being an interface used in mobile and high-speed serial applications to decode display and image data and use it for further processing. The latest technology from MIPI CSI and DSI has paved the way for a new generation of UHD (Ultra High Definition) consumer end products.
The MIPI DSI Tx-Rx Controller IP Cores is capable of handling up to 2.5 Gbps per data lane of D-PHY (V2.0), 10 Gbps over 4 lanes, which is made possible by its programmable data lane configuration. Additionally, it supports features like forward and reverse communication, support for command and video modes, burst and non-burst modes, pulse and event modes, thanks to its extremely flexible architecture. It also has a layered design with a variety of color options, including support for display stream compression and 16, 18, and 36 bpp (DSC). It provides a solution of up to 4 configurable virtual channels, all with lossless data transmission with extensive clock synchronization support.
This MIPI CSI Tx-Rx Controller IP Cores high-speed serial interface protocol for integrating camera subsystems such as RAW image sensors, SOC cameras, image signal processors (ISPs), and bridge devices with host processor such as an application processor in a mobile terminal application. Compliant with MIPI CSI3 V1.0, MIPI M-PHY v2.0 specifications. MIPI UniPro Spec v1.8 with up to 4 configurable MPHY lanes per direction [10Mbps – 5.8Gbps per lane supported]. The CSI controller includes support for a dedicated CPORT for CPC and 2 CPORTs for pixel/embedded data transmission. For a true next-gen feel, it allows interleaving of pixel data from two different sources.
MIPI DSI and CSI Controller IP cores with MIPI D-PHY IP Cores has been used in smartphones, surveillance cameras, automotive cameras, smart watch screens, digital televisions, handheld computers, personal computers and other industrial uses in the semiconductor industry…
In addition to IP MIPI D-PHY Cores, T2M’s wide range of silicon interface IP cores include USB, HDMI, DisplayPort, MIPI (UniPro, UFS, RFFE, I3C), PCIe, DDR, 1G Ethernet, V-by-One, SerDes programmable, OnFi and many more. , available in major Fabs in process geometries as small as 7 nm. They can also be ported to other advanced foundries and process nodes upon request.
Availablity: These semiconductor interface IP cores are available for immediate licensing, either standalone or with pre-integrated controllers and PHYs. For more information on licensing options and pricing, please submit a request / MailTo
About T2M: T2MIPs is the independent global semiconductor technology expert, providing complex semiconductor IP cores, software, KGDs and disruptive technologies enabling accelerated development of your SoCs Wearables, IOT, Communications, Storage, Servers, Networks , TV, STB and Satellite. For more information, visit: www.t-2-m.com