Computers may be getting smaller and more powerful, but they require a lot of energy to run. The total amount of energy the United States spends on computing has increased dramatically over the past decade and is rapidly approaching that of other major sectors, such as transportation.
In a study published online this week, the journal Nature, University of California, Berkeley, engineers describe a major breakthrough in the design of a component of transistors – the tiny electrical switches that form the building blocks of computers – that could significantly reduce their power consumption without sacrificing speed, size or performance. The component, called the gate oxide, plays a key role in turning the transistor on and off.
“We were able to show that our gate oxide technology is better than commercially available transistors: what the trillion-dollar semiconductor industry can do today – we can essentially beat them” , said the study’s lead author, Sayeef Salahuddin, TSMC professor emeritus. of electrical engineering and computer science at UC Berkeley.
This increase in efficiency is made possible by an effect called negative capacitance, which helps reduce the amount of voltage needed to store charge in a material. Salahuddin theoretically predicted the existence of negative capacitance in 2008 and first demonstrated the effect in a ferroelectric crystal in 2011.
The new study shows how negative capacitance can be achieved in an engineered crystal composed of a layered stack of hafnium oxide and zirconium oxide, which is easily compatible with advanced silicon transistors. By incorporating the material into model transistors, the study demonstrates how the negative capacitance effect can dramatically reduce the amount of voltage needed to control transistors and, therefore, the amount of power consumed by a computer.
“Over the past 10 years, the energy used for computing has grown exponentially, already accounting for single-digit percentages of global energy production, which is only growing linearly, with no end in sight” , Salahuddin said. “Usually when we use our computers and mobile phones, we don’t think about the amount of energy we use. But it’s a huge amount, and it will only increase. Our goal is to reduce consumption energy requirements of this basic element of computing, because it reduces the energy requirements of the entire system.
Bringing Negative Capability to Real Tech
State-of-the-art laptops and smart phones contain tens of billions of tiny silicon transistors, and each of them must be controlled by applying a voltage. The gate oxide is a thin layer of material that converts the applied voltage to an electrical charge, which then switches the transistor.
Negative capacitance can increase gate oxide performance by reducing the amount of voltage needed to achieve a given electrical charge. But the effect cannot be achieved with just any material. Creating negative capacitance requires careful manipulation of a material property called ferroelectricity, which occurs when a material exhibits a spontaneous electric field. Previously, the effect was only achieved in ferroelectric materials called perovskites, whose crystal structure is not compatible with silicon.
In the study, the team showed that negative capacitance can also be obtained by combining hafnium oxide and zirconium oxide in an artificial crystal structure called a superlattice, which leads to ferroelectricity and simultaneous antiferroelectricity.
“We found that this combination actually gives us an even better negative ability effect, which shows that this negative ability phenomenon is much broader than originally thought,” the co-first said. Study author Suraj Cheema, a postdoctoral researcher at UC Berkeley. “Negative capacitance doesn’t just occur in the conventional picture of a ferroelectric with a dielectric, which has been studied over the past decade. You can actually make the effect even stronger by designing these crystal structures to harness antiferroelectricity in tandem with ferroelectricity.”
The researchers found that a superlattice structure consisting of three atomic layers of zirconium oxide sandwiched between two single atomic layers of hafnium oxide, totaling less than two nanometers in thickness, provided the best effect. of negative capacity. Since most state-of-the-art silicon transistors already use a 2 nanometer gate oxide composed of hafnium oxide on top of silicon dioxide, and zirconium oxide is also used in silicon technologies , these superlattice structures can easily be integrated into advanced transistors. .
To test the performance of the superlattice structure as a gate oxide, the team fabricated short-channel transistors and tested their capabilities. These transistors would require approximately 30% less voltage while maintaining semiconductor industry benchmarks and no loss of reliability, compared to existing transistors.
“One of the problems that we often see in this type of research is that we can demonstrate various phenomena in materials, but these materials are not compatible with advanced computational materials, and therefore we cannot bring the benefits to the real technology,” Salahuddin said. said. “This work transforms the negative capacitance of an academic subject into something that could actually be used in an advanced transistor.“
Nirmaan Shanker of UC Berkeley is also co-first author of this study. Additional co-authors include Li-Chen Wang, Cheng-Hsiang Hsu, Shang-Lin Hsu, Yu-Hung Liao, Wenshen Li, Jong-Ho Bae, Steve K. Volkman, Daewoong Kwon, Yoonsoo Rho, Costas P. Grigoropoulos, Ramamoorthy Ramesh and Chenming Hu of UC Berkeley; Matthew San Jose, Jorge Gomez, Wriddhi Chakraborty, Patrick Fay, and Suman Datta of the University of Notre Dame; Gianni Pinelli, Ravi Rastogi, Dominick Pipitone, Corey Stull, Matthew Cook, Brian Tyrrell, and Mohamed Mohamed of Lincoln Laboratory at the Massachusetts Institute of Technology; Vladimir A. Stoica of Pennsylvania State University; Zhan Zhang and John W. Freeland of Argonne National Laboratory; Christopher J. Tassone and Apurva Mehta of SLAC National Accelerator Laboratory; Ghazal Saheli and David Thompson of Applied Materials; Dong Ik Suh and Won-Tae Koo of SK Hynix; Kab-Jin Nam, Dong Jin Jung, Woo-Bin Song, Seunggeol Nam and Jinseong Heo of Samsung Electronics; Chung-Hsun Lin of Intel Corporation; Narendra Pariha and Souvik Mahapatra from the Indian Institute of Technology; and Padraic Shafer and Jim Ciston of Lawrence Berkeley National Laboratory.
This research was supported in part by the Berkeley Center for Negative Capacitance Transistors (BCNCT), the DARPA Technologies for Mixed-mode Ultra Scaled Integrated Circuits (T-MUSIC) program, the University of California Multicampus Research Programs and Initiatives (UC MRPI ) and the US Department of Energy, Office of Science, Office of Basic Energy Sciences, Materials Sciences and Engineering Division under Contract No. DE-AC02-05-CH11231 (Microelectronics Co-Design program).